Photomask (in China, called “optical mask”) is the most critical—and also the most easily overlooked—category of consumables in semiconductor manufacturing. In April 2026, Citrini Research analyst Jukan pointed out that “HBM4 brings a photomask outsourcing market that didn’t exist before, and Japanese vendors will become the biggest winners”; within just a week, The Seoul Economic Daily confirmed that this quarter’s photomask outsourcing revenue for Samsung and SK hynix doubled versus the same period last year. This article delivers a complete breakdown of what photomasks are, what kinds HBM4 requires, why Japanese vendors end up taking the lead exclusively, and how investors can get involved.
What is a photomask
A photomask is a template used in semiconductor chip manufacturing to “transfer circuit patterns” onto a silicon wafer. At its core, it is a high-precision quartz glass plate. Its surface is coated with a chromium metal layer tens to hundreds of nanometers thick. Using an electron-beam lithography machine, the designed circuit patterns are etched onto the chromium layer. When the wafer fab runs the lithography steps, the light source passes through the photomask, exposing and developing the circuit patterns on the photoresist material.
An advanced-process chip typically requires 30 to 80 or more photomasks—from design through mass production. Photomasks are a “one-time” process investment: a complete set of photomasks can be used to produce millions of wafers, but whenever product specifications change (a new process node, a new product design), the entire set must be remade. That’s why photomasks have high barriers to entry, high gross margins, but limited total volume—making them a niche market.
Photomask technology tiers and pricing tiers
Photomasks are tiered by process node. The unit price per layer, technical thresholds, and competitive landscape are completely different:
Technology tier | Process node | Price per set | Major suppliers
High-NA EUV | Below 2nm (2027+) | Tens of millions of dollars level | DNP, TOPPAN, Hoya (starting out)
EUV | 3nm / 5nm / 7nm | $200–5M USD | TSMC / Samsung internal + Japanese vendors
DUV / ArF Immersion | 14nm / 28nm | $50–2M USD | DNP, TOPPAN, Photronics
Mature process | 45nm and above | $10–500k USD | Photronics, Taiwan photomask fabs, Chinese vendors
The more advanced the photomask process, the more expensive it is and the harder it is to make—so there are fewer competitors. Above the EUV tier, the level is essentially monopolized by Japanese vendors DNP, TOPPAN, and Hoya, working alongside the internal photomask divisions of TSMC / Samsung / Intel. Mature processes are split among Taiwan photomask firms and international players such as Photronics.
What is HBM, and why does it need photomasks
HBM (High Bandwidth Memory, high-bandwidth memory) is a memory specification that achieves ultra-high bandwidth by vertically stacking multiple layers of DRAM chips, using TSV (through-silicon vias) for vertical interconnection, and pairing it with a base die (logic base chip). Compared with the single-chip structure of traditional DDR5 DRAM, HBM achieves multiple times to tens of times the bandwidth through 3D stacking. It is a key component driving AI GPU computing (Nvidia H100 / H200 / B100 / B200).
HBM manufacturing involves three categories of photomasks: DRAM-chip photomasks for the memory chip body, base-die logic chip photomasks, and TSV via photomasks. Every HBM product is a complete set of photomask tooling, and as generations evolve, the number of photomasks and precision requirements rise in tandem.
HBM4’s technical breakthroughs and new photomask demand
Compared with the previous generation (HBM3E), HBM4 has three major upgrades:
16-Hi stacking: increased from 12 layers to 16 layers. The capacity of each HBM4 reaches 48GB, with bandwidth breaking through 2TB/s
Logic nodes on the base die: for the first time, the base die is made on advanced logic processes like TSMC N3, rather than a traditional DRAM process—this greatly improves the logic of the memory controller, PHY speeds, and power management
Customized design: dedicated specifications for different customers (Nvidia, AMD, Broadcom, Google TPU), no longer standardized products
All three upgrades directly amplify photomask demand: the TSV photomasks required for the 16-Hi stacking need higher precision; base-die photomasks at N3 logic nodes need EUV photomasks; and customized design means each customer needs a new full set of photomasks. As a result, HBM4 shifts from “pure memory manufacturing” to “precision hybrid manufacturing of logic + memory,” and photomask usage jumps from dozens of units in HBM3E to over a hundred.
Why Samsung and SK hynix kick off large-scale outsourcing
Historically, memory makers made their own photomasks—Samsung and SK hynix both have mature internal photomask divisions that previously handled the photomasks needed for DRAM, NAND, and HBM3E. After shifting to HBM4, the outsourcing momentum comes from two directions:
First, pressure from Nvidia Rubin GPU mass-production timing. SK hynix holds a 62% share of the HBM market and is expected to supply for Nvidia Vera Rubin mass production in the second half of 2026; Samsung and Micron are rushing to catch up. The HBM4 divisions at all three companies simultaneously pull internal precision-manufacturing talent, especially senior engineers capable of making base-die logic-node photomasks.
Second, different photomask technology categories. The DRAM photomasks for HBM4 can still be absorbed internally, but base die (TSMC N3 level) photomasks require EUV / High-NA EUV capability. Memory makers’ internal photomask divisions originally specialize in DRAM processes and lack experience with logic-node production. Naturally, this portion flows to Japanese specialized photomask vendors.
The result is the “new market that didn’t exist before,” as Jukan described—memory makers proactively release photomask orders, and the outsourcing targets are Japanese vendors capable of making advanced logic photomasks. Seoul Economic Daily reported that this quarter’s photomask outsourcing revenue doubled or more versus the same period last year, confirming the scale.
Competitive advantages of Japanese photomask vendors
DNP (Dai Nippon Printing) and TOPPAN Holdings are Japan’s two major photomask manufacturers. Both have a “precision manufacturing” gene from a century of printing enterprises. DNP recently partnered with Tekscend to prepare for High-NA EUV photomasks, and announced that it will supply photomasks for Japan’s new startup Rapidus’ 2nm process in 2027. TOPPAN (renamed from Toppan Inc to TOPPAN Holdings in 2023) has an electronics business group that covers TFT LCDs, color filter films, photomasks, and semiconductor packaging.
Their key competitive advantages come from: (1) Japan’s long-term investment in the photomask technology supply chain; (2) deep integration with ASML’s EUV / High-NA EUV equipment; and (3) existing cooperation relationships with TSMC, Samsung, and Intel. Korean and Taiwan photomask companies focus more on mature processes or DUV, making them hard to take on the logic-node orders HBM4 needs.
How investors can participate in this trend
For Japanese stock investors: the direct targets are 7912.T (Dai Nippon Printing) and 7911.T (TOPPAN Holdings). In addition, Hoya (7741.T) also has photomask-related business, but it mainly focuses on EUV photomask substrates (photomask blanks), not the final products. Both recorded multi-year highs in early 2026. Before entering, you should note: whether photomask outsourcing can continue into 2027, and gross margin pressure for non-EUV orders.
For Taiwan stock investors: there are no perfectly comparable listed targets, but you can tap into beneficiary sectors from the periphery. The “photomask concept” includes Yi Hua Dian (易華電), Wits View-KY (維信-KY), and Tong Shin Electric (同欣電), among others; for ABF substrate board and HBM packaging-related names, there are Nan Ya PCB / Kunshan? (欣興), King Yuan Electronics (景碩), and Namchow? (南電). Taiwan Semiconductor Manufacturing Co. (2330), as the foundry partner for HBM4 base dies, also indirectly benefits. The Taiwan photomask group is smaller than Japan’s and is mostly concentrated in mature processes.
For crypto asset investors: HBM4 and AI GPUs directly determine the hardware costs of the next generation of blockchain infrastructure (including AI agent execution, on-chain inference, and zk computation). The underlying logic of this theme is shared with narratives that consume global venture capital—80% of it—such as AI, and infrastructure mining plays like Alcoa × NYDIG: AI compute demand far exceeds the expansion cycle of traditional semiconductors.
Industry chain map: from photomasks to final applications
HBM4’s industry chain has five layers from bottom to top:
Photomask (Photomask): DNP, TOPPAN, and Hoya supply to memory makers and wafer foundries
DRAM / logic wafers: SK hynix (62% market share), Samsung, Micron, TSMC (base die foundry)
Advanced packaging (CoWoS / TSV): TSMC, Amkor, ASE 日月光, etc.
GPU / AI accelerators: Nvidia (H200 / B200 / Rubin), AMD (MI400), Broadcom (TPU foundry)
End users: OpenAI, Anthropic, Google, Meta, data centers of Middle East sovereign wealth funds
Photomasks sit at the very upstream end, so a disruption in a single link can propagate downstream. News that Japanese photomask outsourcing doubles is essentially an early signal of the entire AI hardware investment cycle.
Common questions (FAQ)
What’s the difference between a photomask and photoresist?
A photomask (photomask) is a template used to transfer circuit patterns and can be reused. Photoresist is a coating applied to the surface of a silicon wafer; after the light passes through the photomask, it undergoes chemical changes. Each wafer needs to be coated again. They are both indispensable in the process, but they belong to completely different supply chains: photomasks are led by DNP, TOPPAN, and others; photoresist is led by companies such as Japan’s JSR and TOK.
How is HBM4 different from HBM3E?
HBM4’s three major differences are: 16-layer stacking (HBM3E is 12 layers), base die adopting TSMC N3-class logic processes for the first time (HBM3E is DRAM processes), and customized design (HBM3E is standardized). These three points all raise photomask usage and complexity, and they make base-die photomasks a standalone outsourced requirement.
Why doesn’t DNP make EUV photomasks and only makes mature-process photomasks?
This is a common misconception. In reality, DNP supplies both DUV and EUV photomasks, and it has already planned to supply High-NA EUV photomasks for Rapidus’ 2nm process in 2027. The portion that memory makers outsource to DNP is mainly based on “more mature processes” because memory makers choose to keep their scarcest EUV talent within the core of HBM4, while outsourcing parts that are less critical. DNP’s EUV capability still primarily serves large wafer-foundry customers such as TSMC and Samsung.
Will Samsung and SK hynix outsource permanently?
In the short term (the 2026–2027 Nvidia Rubin mass-production cycle), outsourcing revenue will keep expanding; in the medium term (after 2028), it will depend on whether the two companies’ internal photomask divisions can make up capacity. Historically, Korean memory makers tend to keep core technologies in-house. But HBM4’s base die is on logic nodes, which is too different from the DRAM photomask process Korean firms are historically strong at. So it’s not excluded that they will maintain a long-term division of labor of “memory maker + Japanese photomask vendor.”
Can Taiwan photomask vendors capture HBM4 orders?
Taiwan photomask firms currently focus mostly on mature processes of 28nm and above, and their technology and capacity scale are not comparable to DNP and TOPPAN. But if outsourcing volume continues to expand and Japanese vendors’ capacity is insufficient, Taiwan firms may have opportunities to take on overflow orders. Investors can watch the “Semiconductor Applications” segment growth rate in the second-half-2026 financial reports of photomask companies as the first signal.
What is High-NA EUV? And what’s its relationship with HBM4?
High-NA EUV is ASML’s new-generation lithography machine that starts mass production in 2026. Its numerical aperture increases from 0.33 to 0.55, enabling processes below 2nm. HBM4’s base die itself has not yet used High-NA EUV (the N3 node can still use conventional EUV). However, base dies for HBM5 / HBM6 and beyond will gradually switch. DNP and TOPPAN are investing in High-NA EUV photomask capability to address the market in 2027–2028.
This article: Complete breakdown of HBM photomasks — Why HBM4 makes Japanese DNP and TOPPAN the biggest winners (2026) was first published on Chain News ABMedia.
